CADAPPLETS Applets Illustrating VLSI CAD Algorithms - John A. Nestor

CADAPPLETS Animations of VLSI CAD Algorithms Channel Routing - Left Edge Algorithm Maze Routing Lee Algorithm Lee Algorithm - Multilayer Version A* Algorithm Hadlock's Algorithm Spanning and Steiner Trees Rectilinear Minimum Steiner Tree (Prim's Algorithm) Steiner Tree Demo Borah-Owens-Irwin Steiner Tree Heuristic Placement Floorplanning / Placement Display Floorplanning / Iterative Improvement Floorplanning / Simulated Annealing About this Site This site presents animations of several well-known algorithms for Computer-Aided Design (CAD) of Very Large Scale Integration (VLSI) circuits. VLSI chips are extremely complex and can contain hundreds of millions of transistors. CAD tools are essential because they allow designers to manage this complexity and complete designs in a timely fashion. The animations presented here depict algorithms for the design tasks of placement, which involves the assignment of chip modules to physical locations on a chip surface, and routing, which involves the creation of connections between different modules. This site is hosted by Lafayette College and maintained by Prof. John A. Nestor of Lafayette's Electrical and Computer Engineering Department. Courses hosted at this site

Last updated on July 12, 2007 by John A. Nestor