VLSI Floorplanning / Placement Display

This applet illustrates the problem formulation for VLSI Floorplanning, in which interconnected modules of different sizes and shapes are assigned to positions on a layout surface to form a placement. Connections are specified as nets between terminals on different modules.

The quality of a placment is usually estimated using a weighted sum of cost estimates. Area is estimated as area of the bounding box containing all modules. Wirelength can be estimated in a number of ways, but a common approach (used here) is to compute half the perimeter of the bounding box that contains the terminals of a net. Module overlap is often included in a cost function as a penalty function (these are often used in iterative algorithms like simulated annealing). Finally, congestion estimates the wireability of interconnect regions between placed modules.


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The applet displays modules as yellow rectanges; terminals are marked by small black rectangles. Connections between modules are displayed using red lines. This display of nets is sometimes known as a "rat's nest" diagram. Cost estimates are shown above the placement display. Note that congestion estimates are not included (yet).

The applet allows the user to manipulate a floorplan placement using the mouse - just click on a module and drag it. Modules can also be transformed in the following ways:
  1. Rotate - click mouse over module.
  2. Flip Horizontal - shift-click mouse over module
  3. Flip Vertical - alt-click mouse over module
NOTE:This applet requires the Sun Java Plugin.

For more information about Placement, see a VLSI CAD textbook such as M. Sarrafzadeh and C. K. Wong, An Introduction to VLSI Design, McGraw-Hill, 1996.


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Last updated on July 27, 2001 by John A. Nestor