//    MIPS Single-Cycle Processor Design (based on the P&H subset)
//    ECE 313 - Fall 2002


module mips_pipeline(clk, reset;


    // ********************************************************************
    //                              Signal Declarations
    // ********************************************************************


    // IF Signal Declarations

    wire [31:0] IF_instr, IF_pc, IF_pc_next, IF_pc4;

    // ID Signal Declarations

    wire [31:0] ID_instr, ID_pc4;  // pipeline register values

    wire [5:0] ID_op, ID_funct;
    wire [4:0] ID_rs, ID_rt, ID_rd;
    wire [15:0] ID_immed;
    wire [31:0] ID_extend, ID_rd1, ID_rd2;

    assign ID_op = ID_instr[31:26];
    assign ID_rs = ID_instr[25:21];
    assign ID_rt = ID_instr[20:16];
    assign ID_rd = ID_instr[15:11];
    assign ID_immed = ID_instr[15:0];

    wire ID_RegWrite, ID_Branch, ID_RegDst, ID_MemtoReg,  // ID Control signals
         ID_MemRead, ID_MemWrite, ID_ALUSrc;
    wire [1:0] ID_ALUOp;

    // EX Signals

    wire EX_RegWrite, EX_Branch, EX_RegDst, EX_MemtoReg, 
         EX_MemRead, EX_MemWrite, EX_ALUSrc, EX_Zero;
    wire [1:0] EX_ALUOp;
    wire [2:0] EX_Operation;

    wire MEM_RegWrite, MEM_Branch, MEM_PCSrc, MEM_MemtoReg, 
         MEM_MemRead, MEM_MemWrite, MEM_Zero;


    wire WB_RegWrite, WB_MemtoReg; 


    // EX Signal Declarations

    wire [31:0] EX_pc4, EX_extend, EX_rd1, EX_rd2;  // pipeline register values
    wire [5:0]  EX_rt, EX_rd;

    // ********************************************************************
    //                              IF Stage
    // ********************************************************************


    // IF Hardware

    reg32		IF_PC(clk, reset, pc_next, pc);

    add32 		IF_PCADD(pc, 32'd4, pc_incr);

    mux2 #(32)	IF_PCMUX(MEM_PCSrc, IF_pc4, MEM_btgt, IF_pc_next);

    always @(posedge clk)
    begin
        ID_instr <= IF_instr;
        ID_pc4   <= IF_pc4;
    end

    // ********************************************************************
    //                              ID Stage
    // ********************************************************************

    // ID Signal Declarations












    // sign-extender
    assign ID_extend = { {16{ID_immed[15]}}, ID_immed };

    // branch offset shifter
    assign EX_offset = EX_immed << 2;

    // datapath signals
    wire [4:0] rfile_wn;

    wire [31:0] rfile_rd1, rfile_rd2, rfile_wd, alu_b, alu_out, b_tgt, pc_next,
                pc, pc_incr, br_add_out, dmem_rdata;
    
    
    // control signals

    wire RegWrite, Branch, PCSrc, RegDst, MemtoReg, MemRead, MemWrite, ALUSrc, Zero;
    wire [1:0] ALUOp;
    wire [2:0] Operation;


    // ID Hardware

    ID/EX Pipeline Register
    // break out important fields from instruction

      assign EX_funct = EX_extend[5:0];  
    // module instantiations

    reg32		PC(clk, reset, pc_next, pc);

    add32 		PCADD(pc, 32'd4, pc_incr);

    add32 		BRADD(pc_incr, b_offset, b_tgt);

    reg_file	RFILE(clk, RegWrite, rs, rt, rfile_wn, rfile_rd1, rfile_rd2, rfile_wd); 

    alu 		ALU(Operation, rfile_rd1, alu_b, alu_out, Zero);

    rom32 		IMEM(pc, instr);

    mem32 		DMEM(clk, MemRead, MemWrite, alu_out, rfile_rd2, dmem_rdata);

    and  		BR_AND(PCSrc, Branch, Zero);

    mux2 #(5) 	RFMUX(RegDst, rt, rd, rfile_wn);



    mux2 #(32) 	ALUMUX(ALUSrc, rfile_rd2, extend_immed, alu_b);

    mux2 #(32)	WRMUX(MemtoReg, alu_out, dmem_rdata, rfile_wd);

    control_single CTL(.opcode(opcode), .RegDst(RegDst), .ALUSrc(ALUSrc), .MemtoReg(MemtoReg), 
                       .RegWrite(RegWrite), .MemRead(MemRead), .MemWrite(MemWrite), .Branch(Branch), 
                       .ALUOp(ALUOp));

    alu_ctl 	ALUCTL(ALUOp, funct, Operation);
endmodule