ECE 425 - VLSI Circuit Design
Spring 2007
Laboratory 8 - Combinational Logic Design using Verilog and Synthesis
Last Update: April 9, 2007

1. Introduction

In this lab you will learn how to use the Synopsys tools to synthesize combinational logic circuits inot standard-cell circuit designs using Verilog as an input language.

2. Background

Logic synthesis tools allow designers to compile high-level descriptions of a circuit into standard-cell implementations that can be converted into chip layouts using placement and routing tools.

2.1 Describing Combinational Logic using Verilog HDL

As discussed in class, the basic construct used to describe hardware in Verilog is the module.  Modules describe the interface of a circuit element - its inputs and outputs, and either the structure or function or  of the module.  Structure is described using module instantiation - the creation of submodules which are connected together to implement a desired function.  Function can be described using either assign statements or always blocks.  The assign statement is preferrred for specifying simple logic, while the always block  is needed for more complex functions.  In this experiement, we will use an always block to describe the function of a binary decoder.

The general structure of a module description with an always block is shown below: 

module myLogic(i1, i2, ..., o1, o2, ...);
  input  i1, i2, ...;  
  output o1, o2, ...;
  reg    o1, o2
  always @(i1, i2, ...)
  begin
    ... statements that operate on i1, i2, ...
    o1 = ...;
    ...
    o2 = ...;
    ...
    o3 = ...;
  end
endmodule
Here the combination of the always and @() operators specify a block of logic that activates during simulation when one of the inputs i1, i2, ... changes. When simulating, the model waits for an input to change, then executes the code in the "begin ... end" block, change any outputs for which there are assignment operators, and then loops back to the @() operator to wait for another input change.

Logic synthesis tools are designed to create hardware that mimics the behavior of the simulation model. Specifically, logic will be synthesized so that the output values take on the values that are assigned to them at the end of execution of the block. Even if there are if statements or "for loops" in the begin ... end block, the synthesized logic will be a combinational logic function, providing that each output is assigned a value for all paths through the begin ... end block. In the case where a value is not assigned, synthesis tools will add a latch to "hold" the previous value of the output. This is almost never correct or desirable, so care should be taken to avoid these "latch inferences". We'll discuss this and other issues in class lectures.

For our first Verilog experiment, we'll start with a "skeleton" verilog file for a 2-4 decoder. The goal is to fill in the missing parts of the model, then simulate it to see that it operates properly. Finally we will copy the working Verilog file to the workstations for synthesis and physical design to produce a working standard cell layout.

2.2 Synthesizing Combinational Logic from Verilog

When synthesizing combinational logic, keep in mind that your Verilogger input is a specifiction of a set of outputs that are combinational functions of its inputs. This is a key difference from a software program written in a language like C.

Programming constructs like for loops can be used to make this description more concise, but they do not imply any sequential or procedural behavior. Instead, the Design Compiler expands or "unrolls" loop constructs to form a combinational logic function. The one exception to this rule is when an ouput is not specified for all possible values of the inputs. For example, this can occur when an if-then statement that assigns a value to an uninitialized variable without a corresponding assignment in the else statement. In this case, the Design Compiler will insert a latch to hold the previous value, since the previous value must be preserved if a new value is not specified.

The design compiler works in two steps. In the first step, it translates the Verilog into hardware that implements the logic functions in a straightforward way without regard to cost. In the second step, it optimizes this logic and maps it cells in the MSU SCMOS standard cell library that we are using in our design projects.

A major part of the Design Compiler's capabilities are directed toward optimizing logic under timing constraints. It contains a built-in timing analyzer that finds the longest paths in the synthesized logic network and compares their delay against timing constraints specified by the user. If the constraints are not met, it attempts to modify the design and notifies the user about whether or not the constraints were successfully met. Although this part of the Design Compiler is heavily used in "industrial strength" designs, we will not use it in this lab.

2.3 Using Logic Synthesis and Physical Design Tools

In the lab, you be writing a Verilog input file and using several programs to process this file and synthesize a layout. This section summarizes these tools.

Verilogger - this Windows-based Verilog Simulator has a nice graphical user-interface and is easy to learn. We are using the evaluation version, which supports simulation of only relatively small files.  You can use Modelsim instead if you like.

design_vision - this program provides a graphical user interface to the Synopsys Design Compiler. It runs on the RHEL Linux systems. Using this program you can read a Verilog file, convert it into an unoptimized logic circuit, perform timing analysis (and other analysis tasks), and apply optimizations to reduce layout area and improve timing on selected paths.

sv2mag - this script converts a structural Verilog generated by design_vision or dc_shell to an input that can be read by the Berkeley OctTools package.  It then usees OctTools to perform placement and routing and uses Magic to convert the resulting layout back into a Magic layout.

3. Prelab

A skeleton of a 2-4 binary decoder is shown below. Complete this description by adding appropriate entries to the case statement. Write these entries down on a piece of paper and bring these to lab with you. 
module dec2_4(d_in, d_out);
  input  [1:0] d_in;
  output [3:0] d_out;
  reg    [3:0] d_out;
  always @(d_in)
  begin
    case (d_in)
      2'b00 : d_out = 4'b0001;
      
      /* add additonal cases here */
      
      ...
      default : d_out = 4'bxxxx;
    endcase
  end
endmodule

4. In the Lab

4.1 Creating the File

Using a text editor, enter the Verilog code above (you can copy and paste from the web page if you like) and edit it to implement the full decoder function.  Important: for the synthesis scripts to work properly, this code should be stored in a file with a name that matches the file name, i.e. "dec2_4.v". 

4.2 Simulating a Design

Using a Verilog simulator of your choice, compile and simulate your decoder description to verify that it works properly.  Once it simulates properly, copy the file to the CS file server so that it can be accessed by the Linux systems.

4.2 Synthesizing a Design from Your Verilog File

Log in to one of the Linux systems running RedHat Enterprise Linux (One of the four PCs closest to the aisle).

Copy the "invisible" Synopsys setup file from the CAD account to your home directory:
        cp ~cad/.synopsys_dc.setup .
This should only need to be done once unless it changes.

Start the Synopsys "Design Vision" program using the shell command: 
        design_vision
This will open a window entitled "Design Vision" that is the main interface with the synthesis tools.  Note the menus at the top of the window, the Hierarchy Browser panel, and the Log panel at the bottom of the window (this is where feedback for different commands will appear).

Choose the File->Read menu and choose the your decoder file (i.e. "dec2_4.v") and press the "Open" button.  Check the Log panel for the response - you should see a sequence of messages indicating that the Verilog file has been read successfully, ending with the message "Current design is 'dec2_4'".

When a Verilog file is first read into the Synopsys tools, it is translated into hardware from a generic library called "GTECH".  To see the initial hardware, click on the yellow "gate" button at the top of the window or use the menu "Schematic->New Design Schematic View".  Click on different gates to select them; right-click the mouse and select "Properties" to see the names of the gates.

You are now ready to do design optimization and mapping to our library of gates. Choose the menu "Design->Compile Design..." and press the OK button.  Scroll back through the log file and scan the messages that were printed there.  Then click the "New Schematic" button or use the "Schematic->New Design Schematic" menu to bring up the schematic view again.  Study this schematic and note the differences in this diagram to the previous diagram.  Right-click on some of the new logic gates and use "Properties" to find the part names of the gates.

Print this schematic using the File->Plot menu command and save it for your report.

Save the optimized logic as a structural Verilog file by selecting the  database (".db") file using the File->Save As..." menu item.  Under the format field, select "VERILOG (v)" for the file format, and enter the file name "dec2_4_s.v".  Then exit design_vision using the "File->Exit" menu command.

Examine the contents of the new Verilog file "dec2_4_s.v".  Note it's interface is identical to your original file, but its body now  contains instantiations of a number of standard cell modules (e.g. "norf201").

4.4 Translating Your Sythesized Design to Layout

You will now translate your synthesized design to a Magic layout using a number of physical design tools that run on the Sun workstations.  To do this, use ftp to copy your synthesized Verilog file to your account on the Sun workstation (I will give you an account name at the beginning of lab).

Use telnet to connect from the Linux system to the Sun system "foghorn">
        telnet foghorn.lafayette.edu
The CAD tools for placement and routing are invoked on the Sun using a script called "sv2mag".  Start this program with the command:
        sv2mag dec2_4
Note that this is the name of the module, not the actual file name "dec2_4_s.v".   This script will create a directory "dec2_4_layout" which contains the several Magic files: a "root" file "dec_2_4.mag" and several files that contain layouts for the standard cells.  Log out of the telnet session and use FTP to copy the magic files from this directory back to the Linux system.

Use magic to load your design "dec2_4".  Measure the size of the layout using the "b" (box) command and note it in your report. Next, use plot the layout and print it (black and white is fine) to include in you report.

4.5 Modifying Your Design

This decoder cannot be directly compared to the decoder you designed for the DAC because the decoder for the DAC requires outputs in both inverted and uninverted form.  Modify your Verilog file by adding a second 4-bit output "d_out_bar" that is the logical NOT of "d_out".  Re-simulate your Verilog file to make sure that it simulates properly, and then re-synthesize it and generate a new layout using the steps described previously.  Measure the size of this layout using the "b" (box" command in Magic and note it in your report.  How does this area compare to the area of the decoder that you laid out by hand?  Plot this layout with "flea" to include in with your report.

4.6 Latch Inferences

For a Verilog module containing an always block to be synthesized as combinational logic, each output must be assigned a value under all input conditions.  Failing to do this will create a latch inference because the synthesis tool will create a latch to store output values so that the synthesized design matches the simulation.  To see what a latch inference looks like, remove a "case" and the "default" from your decoder design and repeat step 4.2 (i.e. read your design into design_analyzer again and synthesize ).  Note that the optimize design will now contain latches.

4.7 Additional Designs

Repeat steps 4.1-4.4 for the following modules:
Plot the resulting layouts with flea and note size of each layout in your report.

5. Report

Your report should include the following items: