//-----------------------------------------------------------------------------
// Title         : Test Circuit for Manchester Code Transmitter
// Project       : ECE 491 - Senior Design 1
//-----------------------------------------------------------------------------
// File          : mxtest.v
// Author        : John Nestor  <nestorj@lafayette.edu>
// Created       : 21.10.2004
// Last modified : 21.10.2004
//-----------------------------------------------------------------------------
// Description :
// This module is intended to exercise the Manchester transmitter designed for Lab 5.
// To use this module, instantiate it with input connections that specify the number 
// of bytes to be transmitted (1-4) on the nbytes input and up to 4 data bytes to
// be transmitted connected to inputs d0-d3.  Start out connecting these inputs
// to constants, but later you may want to connect the switches to one of the data inputs.
//
// Connect "run" to a pushbutton input.
// When run=1, this module will send the data bytes to the parallel interface of
// the transmitter and then wait several clock cycles and the retransmit the same
// values as long as run is asserted.
//-----------------------------------------------------------------------------
// Modification history :
// 21.10.2004 : created


module mxtest(clk, reset, run, byte_limit, d0, d1, d2, d3, start, data, ready);
   input        clk;
   input        reset;
   input        run;
   input [1:0]  byte_limit;
   input [7:0]  d0, d1, d2, d3;
   output       start;
   output [7:0] data;
   input 	ready;

   reg [7:0] 	data;
   reg 		start;

   parameter 	WAIT_TIME = 31; 
   parameter    WAIT_BITS = 5;

   //-----------------------------------------------------------------------------
   //        byte counter
   //-----------------------------------------------------------------------------

   reg 		byte_count_enable;
   reg [1:0] 	byte_count;
   reg byte_count_reset;

   always @(posedge clk)
     if (reset | byte_count_reset) byte_count <= 0;
     else if (byte_count_enable) byte_count <= byte_count + 1;
   

   //-----------------------------------------------------------------------------
   //        multiplexer for data
   //-----------------------------------------------------------------------------
   
   always @(byte_count or d0 or d1 or d2 or d3)
      case (byte_count)
	2'd0: data = d0;
	2'd1: data = d1;
	2'd2: data = d2;
	2'd3: data = d3;
	default: data = 8'd0;
      endcase


   //-----------------------------------------------------------------------------
   //        wait cycle counter
   //-----------------------------------------------------------------------------

   reg 		wait_count_enable;
   reg 		wait_count_reset;

   reg [WAIT_BITS-1:0] wait_count;
   wire 	       wait_count_done;
   
   assign 	       wait_count_done = wait_count == WAIT_TIME - 1;

   always @(posedge clk)
     if (reset || wait_count_reset) wait_count <= 0;
     else if (wait_count_enable) wait_count <= wait_count + 1;

   //-----------------------------------------------------------------------------
   //        FSM to generate test signals
   //-----------------------------------------------------------------------------
   
   parameter 	       WAIT_RH=3'd0, WAIT_RL=3'd1, WAIT_DELAY=3'd2;

   reg [2:0] 	       ps, ns;
   
   always @(posedge clk)
     if (reset) ps <= WAIT_RH;
     else ps <= ns;

   always @(ps or run or ready or byte_count or byte_limit or wait_count_done or d0 or d1 or d2 or d3)
      begin
	 start = 1'b0;
	 byte_count_enable = 1'b0;
        byte_count_reset = 1'b0;
	 wait_count_enable = 1'b0;
        wait_count_reset = 1'b0;
	 ns = WAIT_RH;
	 case (ps)
	   WAIT_RH:    // wait for run=1 and ready=1
	     begin
		if (run & ready)
		  begin
		     ns = WAIT_RL;
		     start = 1'b1;
		  end
		else ns = WAIT_RH;
	     end
	   WAIT_RL:   // wait for run=0
	     begin
		start = 1'b1;
		if (ready) ns = WAIT_RL;
		else
 		  begin
		     byte_count_enable = 1'b1;  // increment byte count at END of state
		     if (byte_count != byte_limit) ns = WAIT_RH;
		     else
		       begin
			  ns = WAIT_DELAY;
                       byte_count_reset = 1'b1;
			  wait_count_reset = 1'b1;
		       end
		  end
	     end
	   WAIT_DELAY:
	      begin
		 wait_count_enable = 1'b1;
		 if (wait_count_done) ns = WAIT_RH;
		 else ns = WAIT_DELAY;
	      end
	 endcase
      end
     
endmodule