module bcdcounter_bench;

  // signals for connecting the counter
  reg        clk;
  reg        reset;
  reg        enb;
  wire [3:0] Q;
  wire       carry;

  // testbench variables;
  integer   i;

  // counter instance
  bcdcounter DUT(.clk(clk),.reset(reset),.enb(enb),
                 .Q(Q),.carry(carry));

  task check;
    input [3:0] Q, check_Q;
    input carry, check_carry;

    begin
      if (Q != check_Q)
        $display("Error at time %t: Expected Q=%d, Actual Q=%d",
                 $time, check_Q, Q);
      if (carry != check_carry)
        $display("Error at time %t: Expected carry=%d, Actual carry=%d",
                 $time, check_carry, carry);
    end
  endtask

  // note clock drives both counter and bench
  always #10 clk = ~clk;  
 
   initial begin
    clk = 0;  // necessary to set it to a known value!
    reset = 0;
    enb = 0;
    @(posedge clk);
    // do a reset and check that it worked
    reset = 1;
    @(posedge clk);
    check(Q,0,carry,0);

    // now try counting a few cycles
    #1 reset = 0;
    #1 enb = 1;
    for (i=0; i<9; i=i+1) 
      begin
        @(posedge clk);
        check(Q,i,carry,0);  
      end 
      // now check the carry count should be 9!
    @(posedge clk);
    check(Q,9,carry,1);
    // now check the rollover
    @(posedge clk);
    check(Q,0,carry,0);
    // intentional error - count !=2, carry != 1
    @(posedge clk)
    check(Q,2,carry,0);
    check(Q,1,carry,1);
    repeat (7) @(posedge clk);
    #1 check(Q,9,carry,1);
    #5 enb = 0;
    #2 check(Q,9,carry,0);
    repeat (3) @(posedge clk);
    $stop();  // all done!
  end // initial
endmodule