//-----------------------------------------------------------------------------
// Title         : Seven segment decoder
// Project       : ECE 491 - Senior Design Project 1
//-----------------------------------------------------------------------------
// File          : seven_seg.v
// Author        : John Nestor  <johnnest@localhost>
// Created       : 21.08.2006
// Last modified : 03.09.2004
//-----------------------------------------------------------------------------
// Description
// Seven Segement decoder adapted from David Harris' Verilog tutorial
// Outputs are active low.
//
//-----------------------------------------------------------------------------

module seven_seg(data, segments);
   input  [3:0]	 data;
   output [6:0]  segments;
   
   reg [6:0] 	 segments;
   
   // Output patterns:       abc_defg
   parameter 	 BLANK	= 7'b111_1111;
   parameter 	 ZERO	= 7'b000_0001;
   parameter 	 ONE 	= 7'b100_1111;
   parameter 	 TWO	= 7'b001_0010;
   parameter 	 THREE	= 7'b000_0110;
   parameter 	 FOUR	= 7'b100_1100;
   parameter 	 FIVE	= 7'b010_0100;
   parameter 	 SIX	= 7'b010_0000;
   parameter 	 SEVEN	= 7'b000_1111;
   parameter 	 EIGHT	= 7'b000_0000;
   parameter 	 NINE	= 7'b000_0100;
   
   always @(data)
     case (data)
       4'd0: segments = ZERO;
       4'd1: segments = ONE;
       4'd2: segments = TWO;
       4'd3: segments = THREE;
       4'd4: segments = FOUR;
       4'd5: segments = FIVE;
       4'd6: segments = SIX;
       4'd7: segments = SEVEN;
       4'd8: segments = EIGHT;
       4'd9: segments = NINE;
       default: segments = BLANK;
     endcase
endmodule