Upon completion of this course, students should be able to:

The Design Process

1. Understand the steps of the electronic design process
2. Understand the impact of constraints on the design process
3. Understand economic considerations in electronic design.
   
4. Understand environmental, sustainability, and ethical concerns in electronic design.
   

Digital System Design with FPGAs and Verilog HDL

1. Understand the general structure of common Field Programmable Gate Arrays (FPGAs).
2. Understand the basic constructs of the Verilog Hardware Description Language (HDL).
3. Write Verilog code that can be reliably synthesized into combinational logic, sequential logic, and Finite State Machines (FSMs).
4. Write a Verilog testbench that verifies the correctness of a design using self-checking procedural code.
5. Recognize and avoid common Verilog coding pitfalls.
6. Understand the datapath / controller paradigm for designing complex digital systems.
7. Understand the timing of digital systems in FPGA-based systems, especially as they limit clock frequency.
8. Understand the purpose of synchronizers in sequential logic designs.
9. Understand how handshaking is used to reliably transfer data and control information between sequential circuits operating off different clock signals.

Data Communications and Networking

1. Understand the concept of Manchester encoding for data transmission.
2. Understand the concept of differential line drivers for enhanced reliability in transmission.
3. Understand simple asynchronous serial communications protocols and create circuits that can interface to these protocols.
4. Understand the protocol of an Ethernet network.
5. Understand the layers of the Open Systems Interconnection (OSI) model for networking.