Matthew A. Watkins

Main Teaching Research Publications

Research

Current Research

Managing Heterogeneous Architectures

Single-chip heterogeneous have become an attractive solution to provide power and performance efficiency and adaptability in modern computing systems. Common forms of heterogeneity include incorporating processing cores with different power and performance trade-offs and incorporating both CPUs and graphics processing units (GPUs) on die. Dynamic heterogeneity is also possible through dynamic voltage and frequency scaling (DVFS). To realize the full potential of these systems, however, the different elements must be intelligently managed and applications must be appropriately scheduled among the different computing elements.

Dynamic Translation for Reconfigurable Architectures

There have been numerous proposal for integrating reconfigurability into multiprocessors. The reconfigurable elements generally do not utilize the same instructions as the base processor. This means that a program must be reworked to be able to take advantage of the reconfigurability. Many proposals ignore this aspect. Of those that do consider it, most look at recompiling the workload to make use of the reconfigurable elements. Another options is to dynamically translate relevant regions of code to make use of reconfigurability while the program is executing. This eliminates the need to recompile the application. It also has the potential to take advantage of information not available at compile time and allow a system to take advantage of more capable reconfigurable elements as they become available in the future. Performing these optimizations efficiently on-the-fly is non-trivial, but has the potential to greatly improve the appeal and, in some cases, the performance offered by integrated reconfigurability.

Past Research

Reconfigurable CMP Architectures

Recent trends in processor design have been towards including multiple cores on a single die. The best way to organize these chip multiprocessors (CMPs) remains an open question. On interesting option is to include a reconfigurable fabric on die that can dynamically create the functionality best suited to the running application. A number of designs have been proposed in the past for single core systems. The power and area costs of most of these designs have been prohibitive and so have generally not been adopted in main stream general purpose processors. With the advent of CMPs, a single fabric can be shared among multiple cores, amortizing the area and power costs of the fabric while also increasing the overall utilization of the fabric. My research focuses on a number of aspects related to shared reconfigurable fabrics, including the best organization for such designs, thread scheduling for shared fabrics, and unique uses of reconfigurable fabrics relative to parallel applications.

On-chip Optical Interconnects

As technology continues to scale, the delay of on-chip wires relative to logic gates continues to increase. Efficient communication between cores on a die will be critical to getting the most performance out of future CMPs. Optical interconnects provide one possible solution to this problem as they provide lower latency and higher bandwidth communication than their electrical counterparts. Optical interconnects also face a number of design and fabrication limitations. We look at the best way to use optics on-chip given these features and restrictions.