Lab Assignments

• Lab 1 - Spartan 3 Board Familiarization; Verilog Comb. Logic
• Verilog file: s3board.v
• Verilog file: seven_seg.v
  
• Constraint file: s3board.ucf
• Lab 2 - Verilog Sequential Logic
• Verilog file: Debounce circuit for pushbutton inputs
• Lab 3 - Simulation and Testbenches
  
• Verilog file: bcdcounter.v (BCD Counter Example)
  
• Verilog file: bcdcounter_bench.v (BCD Counter Testbench)
• Lab 4 - RS-232 Transmitter


• Lab 5 - RS-232 Receiver


• Lab 6 - Manchester Code Transmitter
• Verilog file: mxtest.v - transmitter test file
• Lab 7 - Manchester Code Receiver
• Verilog file: sasc.v - 4-stage FIFO from www.opencores.org
• File directory: fifo_blockram - Block RAM FIFO from Xilinx application note.
• Project - WimpNet 2006
• Verilog file: mem.v - file to infer buffer Block RAM
• Verilog file: crc.v - CRC calculation
  

Reference Information

• Spartan-3 Starter Kit Board User Guide (copy available in Lab)
  
• Spartan-3 Data Sheets (copies available in Lab)
• "Using Block RAM in Spartan 3 FPGAs", Xilinx Application Note XAPP463 (copy available in Lab)
  
• Texas Instruments SN75HVD12 RS-485 Driver Data Sheet (copy available in Lab)